(1) Field of the Invention
The present invention relates to a semiconductor memory device such as a memory card, and a semiconductor memory system including the semiconductor memory device. The present invention especially relates to a technique of preventing decreased endurance reliability caused by performance degradation of a nonvolatile memory in a semiconductor memory device.
(2) Description of the Related Art
Conventionally, a semiconductor memory device such as a Secure Digital (SD) card which is a card-type recording medium including a flash memory is microminiature and super-slim, and is widely used to store data such as images in a digital camera, a mobile appliance, and so on because of its ease of handling.
The flash memory included in such a semiconductor memory device is a nonvolatile memory in which data can be erased and rewritten in units of blocks of a fixed size. One example of the flash memory is a NAND-type flash memory. There are two modes of storing data in the NAND-type flash memory: a Single-Level Cell (SLC) mode of storing two-valued data in a memory cell; and a Multi-Level Cell (MLC) mode of storing data more than two values in a memory cell. In the SLC mode, two voltage levels are associated with 0 and 1, so that two-valued data of one bit is stored per cell. In the MLC mode, for example, four voltage levels are associated with 0, 1, 2, and 3, so that four-valued data is stored per cell.
The following describes a relation between the number of electrons accumulated in a floating gate of a SLC flash memory (hereafter referred to as “flash memory”) and a threshold voltage (Vth), with reference to FIG. 13.
FIG. 13 is a diagram showing a structure of one cell of the flash memory. FIG. 13(a) is a diagram showing an initial state before data is written, where no electron's charge is accumulated. FIG. 13(b) is a diagram showing a state after data is written, where an electron's charge is accumulated.
As shown in FIGS. 13(a) and 13(b), the flash memory has a structure in which N-channel source electrode 1005 and drain electrode 1006 are formed on a P-channel substrate 1007, and a tunnel oxide film 1004, a floating gate 1003, an oxide insulation film 1002, and a control gate 1001 are stacked between the source electrode 1005 and the drain electrode 1006.
Thus, in the flash memory, an electron's charge retaining region called the floating gate 1003 is included in the transistor, unlike a volatile Dynamic Random Access Memory (DRAM). A voltage threshold when a current flows changes according to a state of the electron's charge accumulated in the floating gate 1003, in the flash memory. In the initial state before data is written, no electron's charge is accumulated in the floating gate 1003 as shown in FIG. 13(a). In the state after data is written, on the other hand, electrons are accumulated in the floating gate 1003 as shown in FIG. 13(b).
In the flash memory, the voltage (threshold) when a current flows changes according to whether or not electrons are accumulated in the floating gate 1003. In the case of the SLC flash memory that expresses one bit of information per cell, there are two states of the threshold voltage when a current flows according to the amount of electrons. For example, a potential is low when no electron is accumulated as shown in FIG. 13(a), whereas the potential increases as electrons are accumulated as shown in FIG. 13(b). Accordingly, electron accumulation can be controlled in two states so as to be within a predetermined potential threshold. This enables one bit of data to be stored in one memory cell.
Moreover, the tunnel oxide film 1004 having an insulation function is used in the flash memory, in order to retain electrons accumulated in the floating gate 1003. Upon writing or erasing data, electrons pass through the tunnel oxide film 1004. This being so, when data is repeatedly rewritten, the tunnel oxide film 1004 degrades due to injection and extraction of electrons. As a result of repeated damage to the tunnel oxide film 1004, the tunnel oxide film 1004 eventually becomes unable to function as an insulator.
Meanwhile, in the MLC mode of storing four-valued data per cell, there are four states of the threshold voltage when a current flows according to the amount of electrons. Since the threshold voltage is controlled not only by whether or not electrons are accumulated but also by the amount of electrons, it is susceptible to a change in electron amount caused by the degradation of the tunnel oxide film 1004 upon rewriting.
Thus, the flash memory has structural characteristics of being limited in rewrite frequency. In view of this, conventionally the rewrite frequency of the flash memory is stored and managed in the semiconductor memory device (for example, see Japanese Unexamined Patent Application Publication No. 2005-284659).
The following describes a conventional method of managing the rewrite frequency of the flash memory, with reference to FIG. 14. FIG. 14 is a diagram showing a structure of a conventional semiconductor memory system.
As shown in FIG. 14, the conventional semiconductor memory system includes a host 1100 such as a Personal Computer (PC), and a semiconductor memory device 1110 such as an SD card that is capable of retaining data in an internal semiconductor memory.
The conventional semiconductor memory device 1110 includes: an interface conversion unit (hereafter referred to as “IF conversion unit”) 1120 that receives access from the host 1100; a flash memory 1140 that stores data; a flash memory access unit 1130 that writes data to or reads data from the flash memory 1140; and a memory information management unit 1150 that manages information of the semiconductor memory device 1110. The memory information management unit 1150 includes a rewrite frequency storage unit 1156 that stores a rewrite frequency of the flash memory 1140.
When the semiconductor memory device 1110 receives a data write request from the host 1100, the IF conversion unit 1120 converts it to a write sequence to the flash memory 1140, and writes data to the flash memory 1140. Moreover, the memory information management unit 1150 increments the rewrite frequency stored in the rewrite frequency storage unit 1156.
To check the rewrite frequency, the host 1100 independently issues a request (device unique command) for obtaining the rewrite frequency, to the semiconductor memory device 1110. The IF conversion unit 1120 analyzes the command for obtaining the rewrite frequency, and returns the rewrite frequency stored in the rewrite frequency storage unit 1156 in the memory information management unit 1150 to the host 1100, as a response to the command for obtaining the rewrite frequency.
However, in the above-mentioned structure of the conventional semiconductor memory system, in the case where the type of semiconductor memory device changes such as when an SD card of a new type is produced by a manufacturer, the host needs to independently issue a command for obtaining the rewrite frequency, for each type of semiconductor memory device.
Thus, the conventional semiconductor memory system has a problem that an access method for obtaining the rewrite frequency needs to be changed for each type of semiconductor memory device, and semiconductor memory devices of different types cannot be accessed in a uniform manner.